1. Technical Field
The present invention relates to a data input circuit and method of inputting data, and in particular, to a data input circuit of a semiconductor memory apparatus and method of inputting the data that is capable of reducing power consumption.
2. Related Art
Generally, a semiconductor memory apparatus includes a write latency control unit to generate a buffer enable signal. The semiconductor memory apparatus further includes a data input buffer to perform a buffering operation on input data depending on whether the buffer enable signal is enabled or not.
When a write command is input, data is input after predetermined cycles of a clock. In this case, a write latency indicates the number of cycles of the clock when the data is input. Generally, the length of the write latency is 1 to 7. A write latency signal is allocated beforehand for each of the lengths of the write latency.
The write latency control unit enables a low enable signal when a row active command is input, and disables the low enable signal when a row precharge command is input. Further, the write latency control unit enables the write enable signal when the write command is input, and disables the write enable signal when a burst end signal is input. The row enable signal or the write enable signal is used as the buffer enable signal.
When the length of the write latency is short (for example, 1 to 3), if the write latency control unit enables the buffer enable signal according to input of the write command, an undesirable effect such as the delay of input of the data at the data input buffer occurs. Thus, erroneous operation such as a timing error between the buffer enable signal and the input data may occur. Therefore, when the length of the write latency is short, the row enable signal is output as the buffer enable signal, in order to increase a timing margin between the buffer enable signal and the input data because the row active command is enabled earlier than the write command.
In contrast, when the length of the write latency is long (for example, 4 to 7), the write enable signal is output as the buffer enable signal. Since an enable period of the row enable signal is longer than an enable period of the write enable signal, it may reduce the power consumption.
Such a data input circuit for a semiconductor memory apparatus is designed to accommodate the use of a high frequency clock. The semiconductor memory apparatus uses a DLL (Delay Locked Loop) off mode in order to reduce the power consumption. When the semiconductor memory apparatus enters the DLL off mode, a DLL circuit does not operate and an external clock having a low frequency is transmitted to internal individual regions.
When the semiconductor memory apparatus uses the low frequency clock, that is, the same as the DLL off mode, the enable period of the row enable signal becomes longer as the period of the clock is lengthened. In this case, if the write latency is short, the enable period of the buffer enable signal becomes longer, which increases the power consumption. However, currently, there is no technique for reducing the unnecessary power consumption, resulting in continuous current consumption.